DSP56311EVM【PDF 93/360 页】KIT EVALUATION FOR DSP56311

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PLL Control Register (PCTL)

Table 4-6. Interrupt Source Priorities Within an IPL (Continued)

Priority

Lowest

SCI receive data

SCI transmit data

SCI idle line

SCI timer

TIMER0 overflow interrupt

TIMER0 compare interrupt

TIMER1 overflow interrupt

TIMER1 compare interrupt

TIMER2 overflow interrupt

TIMER2 compare interrupt

EFCOP Data Input Buffer Empty

EFCOP Data Output Buffer Full

Interrupt Source

4.5 PLL Control Register (PCTL)

The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by configuring

the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write register that directs

the on-chip PLL operation. (See Figure 4-5 .)

23

PD3

11

MF11

22

PD2

10

MF10

21

PD1

9

MF9

20

PD0

8

MF8

19

COD

7

MF7

18

PEN

6

MF6

17

PSTP

5

MF5

16

XTLD

4

MF4

15

XTLR

3

MF3

14

DF2

2

MF2

13

DF1

1

MF1

12

DF0

0

MF0

Figure 4-5. PLL Control Register (PCTL)

Table 4-7 defines the DSP56311 PCTL bits. Changing the following bits may cause the PLL to

lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF.

Table 4-7. PLL Control Register (PCTL) Bit Definitions

Bit Number

23–20

Bit Name

PD[3–0]

Reset Value

0

Predivider Factor

Description

Define the predivision factor (PDF) to be applied to the PLL input frequency.

The PD[3–0] bits are cleared during DSP56311 hardware reset, which

corresponds to a PDF of one.

19

COD

0

Clock Output Disable

Controls the output buffer of the clock at the CLKOUT pin. When COD is set,

the CLKOUT output is pulled high. When COD is cleared, the CLKOUT pin

provides a 50 percent duty cycle clock.

DSP56311 User’s Manual, Rev. 2

Freescale Semiconductor

4-19

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